1. Field of the Invention
The present invention relates to a digital signal processor, and more specifically to a technique for realizing a recursive digital filter by a parallel arithmetic processing of microprocessor type hardware device.
2. Description of Related Art
In a microprocessor, recently, a divided-ALU operation instruction (also called a group instruction) is beginning to be adopted in order to speed up an image processing such as MPEG (Moving Picture Experts Group).
For example, the divided-ALU instruction is an instruction for utilizing one 64-bit ALU (Arithmetic and Logical Unit) as four 16-bit ALUs, as shown in FIG. 1.
An example of the divided-ALU instruction is proposed by Craig Hansen, "Architecture of a Broadband Mediaprocessor", IEEE Proceedings of COMPCON '96, 1996, pages 334-340, the content of which is incorporated by reference in its entirety into this application.
By adopting the divided-ALU, it is possible to easily speed up a signal processing having data parallelism and an image processing. An example of this is also proposed by Curtis Abbott et al, "Broadband Algorithms with the MicroUnity Mediaprocessor", IEEE Proceedings of COMPCON '96, 1996, pages 349-354, the content of which is incorporated by reference in its entirety into this application.
However, even if the divided-ALU is adopted, the speed-up of the processing is not so easy in the case that a signal flow is recursive and is difficult to parallelize, as in an IIR (infinite impulse response) digital filter.